| 摘要 |
<p>A manifold array architecture achieves configurable instruction set optimization by using an instruction abbreviation process to reduce memory and power usage for applications in high volume portable products. A standard instruction is reduced to a smaller length instruction format. An application programmed using native instructions (301) is verified before being analyzed by an abbreviation tool (303). The instruction abbreviation process allows different program reduction optimizations tailored for each application program. The process develops an optimized instruction set for the intended application. The functionally equivalent abbreviated instructions are stored in a significantly smaller memory and are fetched for dynamic translation in a sequence controller. Since the instruction set is determined for the specific application, an optimized processor design can be easily produced (305).</p> |
