| 摘要 |
An apparatus and method is provided for reducing the area of integrated circuits using cells with multiple unrelated gates. A netlist is generated which includes cells and interconnecting nets. Each cell represents a circuit and each net represents an interconnection between cells. Combinable cells of the netlist are paired to create a list. A combinable cell represents a circuit having at least one transistor formed on a substrate area. This transistor includes a diffusion layer directly coupled to a voltage source via a diffusion contact, wherein the diffusion contact is positioned adjacent an outer edge of the substrate area. A combinability score is calculated for each pair of combinable cells of the list. Each combinability score is calculated as a function of the number of nets representing direct or indirect interconnections between a pair of combinable cells. The pair of combinable cells corresponding to the highest combinability score is removed from the netlist. Thereafter, a combined cell is added. This combined cell, prior to addition to the netlist, represents at least first and second circuits. Inputs and outputs of the first circuit are electrically isolated from inputs and outputs of the second circuit.
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