Control circuit for a bit line equalization signal in semiconductor memory

摘要

A control circuit for a bit line equalization signal in semiconductor memory which equalizes each initial voltage at a bit line and bit bar line, providing sufficient line driving voltage by producing a bit line equalization signal of a higher voltage level if a power voltage level for the circuit has been reduced. A delaying part supplied with a first bit line equalization signal of a first voltage level and outputs the first bit line equalization signal after a period of time. A controller generates a second bit line equalization signal from both the first bit line equalization signal and an output signal of the delaying part. A charge pump raises the voltage level of the first bit line equalization signal up to a second voltage level based on the first bit line equalization signal and the second bit line equalization signal.