发明名称 EMITTER/FOLLOWER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress the peaking of frequency characteristics generated due to the parasitic inductance of base wiring and the input capacitance of an emitter/follower in an emitter/follower circuit. SOLUTION: In an emitter/follower circuit including an emitter/follower transistor Tr1 and an emitter load resistance RE1, a by-pass circuit CIR1 is provided between the base terminal and emitter terminal of the transistor Tr1, and the input capacitance of the emitter/follower circuit is reduced by the input impedance of the by-pass circuit CIR1 so that the peaking of frequency characteristics can be suppressed.
申请公布号 JP2001111361(A) 申请公布日期 2001.04.20
申请号 JP19990291111 申请日期 1999.10.13
申请人 NEC ENG LTD 发明人 SHINOZUKA TOSHIYUKI
分类号 H03F3/50;H03F3/195;(IPC1-7):H03F3/50 主分类号 H03F3/50
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