NON-VOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME

摘要

PURPOSE: A non-volatile memory and a method for fabricating the same are provided to lower a voltage applied to an erasing gate by using a vector sum of a bit line and an erasing gate. CONSTITUTION: An isolation layer(32) is formed in a predetermined interval on a semiconductor substrate(31). A bit line(33) is formed on the semiconductor substrate(31) including the isolation layer(32). The bit line(33) is located on a multitude of line of a vertical direction of the isolation layer(32). A buried n+ layer(35) for bit line is buried into the semiconductor substrate(31) between the isolation layers(32). The buried n+ layer(35) for bit line is contacted with a lower side of the bit line(33). A floating gate(36) is formed by inserting a gate oxide layer(34) into one side between the isolation layers(32). A control gate(38) is formed by inserting an interlayer dielectric(37) into an upper side of the floating gate(36). An erasing gate(41) is formed by inserting a gap gate oxide layer(39) and the second insulating layer sidewall on upper sides of the control gate(38) and the floating gate(36).