发明名称 Analog delay line implemented with a digital delay line technique
摘要 An analog delay line uses an analog-to-digital (A/D) converter which converts an analog signal into a plurality of digital signals. Digital delay lines, each including a series of digital delay elements, delay the respective digital signals. A digital-to-analog (D/A) converter converts the digital signals back into a delayed analog signal.
申请公布号 US6218880(B1) 申请公布日期 2001.04.17
申请号 US19970993519 申请日期 1997.12.18
申请人 LEGERITY 发明人 RELPH RICHARD
分类号 G11C27/00;H03K5/00;H03K5/13;(IPC1-7):H03H11/26 主分类号 G11C27/00
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