| 摘要 |
PURPOSE: A DRAM cell device and a manufacturing method therefor are provided to reduce leaking current in a high charging density. CONSTITUTION: A first substrate(1) having a memory cell comprising one transistor and one capacitor and having recessed parts(V) is installed. The surface has a capacitor dielectric(KD) and is filled with a memory node(SP). The transistor is arranged on a second substrate(2). A source/drain area(S/D1) is brought into contact with the surface(O1) of the substrate(2) and a source/drain area(S/D2) is brought into contact with the different surface(O2) of the substrate(2). The substrates(1 and 2) are mutually connected so that an isolation layer(1) is arranged between them. The layer is brought into contact with the memory node and the surface(O2). The substrate(2) has a first trench(G1), isolates the source/drain area, and cuts the isolation layer. A contact is arranged in the isolation layer and it is brought into contact with G1, S/D2 and SP.
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