| 摘要 |
PROBLEM TO BE SOLVED: To provide a DRAM with reduced bit line interference noises, having a cell array of an open bit-line system. SOLUTION: This cell array of an open bit-line system has an SGT cell structure. A memory cell is formed in each intersection of word lines 14 and bit lines 16. Each memory cell along a bit line is regarded as an NMOS cell MN which uses an NMOS transistor as its transfer gate and each memory cell along another bit line adjacent to the bit line is regarded as a PMOS cell MP, which use a PMOS transistor as its transfer gate. |
