| 摘要 |
<p>PURPOSE:To authorize a timepiece operation even in a long time power failure, by stopping a first oscillation circuit which detects a power failure signal from the outside, and generates the clock of a CPU at time of power failure, keeping a second oscillation circuit at an operating state, and counting the output of the second oscillation circuit at a counter circuit. CONSTITUTION:At time of the power failure, a signal of low level is inputted to a power failure signal input terminal. At this time, a control circuit outputs the signal to set the first oscillation circuit 1 at a stop state, and the second oscillation circuit 2 at the operating state. In other words, only the second oscillation circuit 2 is started to operate, and the output is derived to the counter circuit 4 via a frequency-division circuit 7, and counting at time of the power failure is performed. Next, when a High level is inputted to the power failure signal input terminal again (this state means the recovery of the power failure), the control circuit 8 sets the first oscillation circuit at the operating state, and the second oscillation circuit at the stop state again. Afterwards, the content of the counter circuit 4 is read out via a data bus, and is added on a timepiece data before the power failure, and after addition, a timepiece clock outputted from a frequency-division circuit 6 is counted again, then the update of the timepiece is performed.</p> |
