Circuit for determining latency of buffer circuit generates latency interval and latency indication from clock signal and from test signal derived from clock signal with delay

摘要

The circuit has a latency interval definition stage (20) that receives a clock signal (CLK) and generates at least one latency interval definition signal that defines at least one latency interval. A latency indication stage (30) receives the definition signal(s) and a test signal (Del2) delayed relative to the clock signal by a defined time and generates a latency indication from them. The test signal is derived from the clock signal. Independent claims are also included for the following: a variable latency buffer circuit, a memory component and a method of determining latency.