| 摘要 |
PURPOSE: A cell selection circuit is provided to reduce a lay-out area related to a word line driver by decreasing the number of gates for constituting the word line driver in a memory device. CONSTITUTION: The circuit includes an address decoding control unit(210), a logic gate unit(220) and a word line driving unit(230). The address decoding control unit activates a control signal(MRBLK) for decoding an address signal when selection signals(MBLK,RBLK) for respectively selecting a main cell and a repair cell are mutually an opposite level. The logic gate unit logically combines external address signals(X0TN-X2TN) when the output of the address decoding unit is low. The word line driving unit inputs an output of the logic gate unit, outputs word line driving signals(MWL,RWL) and activates one of the word line driving signal in response to the selection signals.
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