发明名称 APPARATUS FOR ANALYZING DATA CAPACITY IN HDLC COMMUNICATION PATH
摘要 PURPOSE: An apparatus for analyzing a data capacity in an HDLC(High-level Data Link Control) communication path is provided to calculate usage rates of substantial data, when an HDLC communication system communicates with external system through the HDLC communication path, and to analyze the data capacity relating to the HDLC communication path, then to decide whether data and transmission speeds are increased or decreased. Therefore, the HDLC communication path is efficiently operated. CONSTITUTION: A transmission data recognizer(11) counts high levels relating to transmission data to decide whether the transmission data exists. If so, the recognizer(11) outputs transmission clocks during the transmission data existence. A transmission data clock counter(12) counts the transmission clocks. A transmission clock counter(13) counts the transmission clocks only. A transmission efficiency displayer(14) calculates data transmission rates with counting values of the counter(12) and the counter(13), and analyzes a transmission data capacity relating to an HDLC(High-level Data Link Control) communication path, then displays the capacity. A receiving data recognizer(15) counts high levels relating to receiving data to decide whether the receiving data exists, and outputs receiving clocks during the receiving data existence. A receiving data clock counter(16) counts the receiving clocks. A receiving clock counter(17) counts the receiving clocks only. A receiving efficiency displayer(18) calculates data receiving rates with counted values of the counters(16,17), and analyzes a receiving data capacity, then displays the capacity.
申请公布号 KR20010027335(A) 申请公布日期 2001.04.06
申请号 KR19990039036 申请日期 1999.09.13
申请人 HYNIX SEMICONDUCTOR INC. 发明人 HA, HYEON U;OH, JEONG HUN
分类号 H04B1/76;(IPC1-7):H04B1/76 主分类号 H04B1/76
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