CBR COUNTER WITHIN D-RAM SEMICONDUCTOR DEVICE

摘要

PURPOSE: A CBR(CAS Before RAS) counter within a D-RAM(Dynamic Random Access Memory) semiconductor device is provided to perform the CBR counting from a predetermined address so that the CBR counter is accurately tested. CONSTITUTION: The CBR counter(101) includes a MRS logic circuit(111), a pulse generator(121), a CBR counter logic part(131) and a row-address related circuit(141). The MRS logic circuit(111) generates a control signal(P1) for resetting the CBR counter(101). The pulse generator(121) generates a reset signal(RESETCBRB) according to the control signal(P1) activates. The CBR counter logic part(131) counts input clock pulses(CNTP), and the count signal(CNTi) is resetted according to the reset signal(RESETCBRB). The row-address related circuit(141) generates a row address signal(RRAi) for counting according to an input row address signal(RAi). The row address signal(RRAi) is resetted according to the reset signal(RESETCBRB).