发明名称 DEVICE AND METHOD FOR SYNTHESIZING AND VERIFYING LOGIC AND RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To reduce the man-hour required for synthesizing and verifying a plurality of net lists from logical descriptions. SOLUTION: A means 1 generates a net list B from a logical description A and a means 2 verifies the consistency between the description A and list B. Means 3 and 4 generate net lists DI, etc., corresponding to different signal names, and logical descriptions F1, etc., by converting the signal names in the list B and description A in accordance with a signal name corresponding card file C in which different signal names are arranged correspondingly to the signal names in the list B. A means 5 detects the difference in signal name between the net list B and net lists DI, etc., and outputs a net list signal name difference file E in which the signal names are arranged. A means 6 detects the difference in signal name between the logical description A and logical descriptions F1, etc., and outputs a logical description signal name difference file G in which the signal names are arranged. A means 7 verifies the consistency between the files E and G.
申请公布号 JP2001092869(A) 申请公布日期 2001.04.06
申请号 JP19990269802 申请日期 1999.09.24
申请人 NEC ENG LTD 发明人 HASHIDA TOUSHI
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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