发明名称 TWISTED BITLINES ARCHITECTURES
摘要 <p>An integrated circuit comprising first and second adjacent signal line pairs (310 and 320) is described. The signal line pairs comprise diagonal signal paths (311p, 312p; 321p and 322p) with directional changes (335). The first signal line pair comprises m twists (340), where m is a whole number ≥ 1, and the second signal line pair comprises n twists (360 and 361), where n is a whole number ≠ m.</p>
申请公布号 WO2001024266(A1) 申请公布日期 2001.04.05
申请号 US2000025275 申请日期 2000.09.14
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址