| 摘要 |
An adder, a processor (such as a microprocessor or digital signal processor), and methods of adding in such adder or processor. In one embodiment, the adder includes: (1) a first and second units in a first logic layer, the first unit receiving first and second addend and augend bits and generating therefrom a first single group-carry-generate bit and first and second carry-propagate bits, the second unit receiving third and fourth addend and augend bits and generating therefrom a second single group-carry-generate bit and third and fourth carry-propagate bits and (2) a third unit in a second logic layer, coupled to the first and second units, that receives the first and second single group-carry-generate bits and the first, second, third and fourth carry-propagate bits and generates therefrom resulting group-carry-generate and group-carry-propagate bits.
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