| 摘要 |
PURPOSE: A circuit for dividing a sending clock is provided to prevent the distortion of the oscillating frequency generated in dividing a sending clock and to apply it to a PLL circuit of the exchange system by the simple structure of the circuit. CONSTITUTION: A circuit for dividing a sending clock includes a phase control portion(11), oscillators(22, 33), RF switches(44, 55), a RF connector(66), an amplifier(77). The phase control portion(11) outputs many phase control signals. The oscillators(22, 33) output the radio frequency signal of the appointed band oscillated in the phase according to the phase control signal. The RF switches(44, 55) output the radio frequency signal by switching selectively. The RF connector(66) connects the switching output radio frequency signal. The amplifier(77) amplifies the connected radio frequency signal to the fixed level and outputs it.
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