发明名称 METHOD FOR MANAGING INTER PROCESSOR COMMUNICATION TRANSMISSION QUEUE OF PROCESSOR COMMUNICATION CONTROLLER BOARD ASSEMBLY IN FULL ELECTRONIC TELEPHONE EXCHANGE
摘要 PURPOSE: A method for managing the inter processor communication transmission queue of a PCCA(Processor Communication Controller board Assembly) in a full electronic telephone exchange is provided to replace an existing DMA(Direct Memory Access) queue by defining 64 transmission buffer identifiers and configuring them in the form of a ring buffer. CONSTITUTION: A transmission control board consists of a memory(10) and an SCC(Serial Communication Controller)(40). The memory(10) is composed of a DRAM or an SRAM comprising a processor window list, standby messages, and 64 transmission buffer identifier blocks. The SCC(40) contains a FIFO(First-In First-Out buffer)(30) that transmits a message as soon as it is inputted. The FIFO(30) is of a 16-byte self-contained type. The 64 transmission buffer identifiers of the memory(10) are defined by variable declaration. The SCC(40) manages these 64 transmission buffer identifiers.
申请公布号 KR100293363(B1) 申请公布日期 2001.04.03
申请号 KR19970075678 申请日期 1997.12.27
申请人 HYNIX SEMICONDUCTOR INC. 发明人 JANG, IN JIN
分类号 H04Q3/54;(IPC1-7):H04Q3/54 主分类号 H04Q3/54
代理机构 代理人
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