发明名称 Method for analyzing probe yield sensitivities to IC design
摘要 A method for predicting yield limits of semiconductor wafers in a factory, including the steps of generating a wafer probe test pareto, determining a histogram of the distribution from a selected group from the wafer probe test pareto, extracting parametric data from a database from the histogram, screening the parametric data for values of the parametric data outside of a predetermined range, determining if an average value of the screened parametric data shows a sensitivity to variations in the parametric data, determining specification limits of the screened parametric data, and using the specification limits to form an operating window to show the sensitivity.
申请公布号 US6210983(B1) 申请公布日期 2001.04.03
申请号 US19990333787 申请日期 1999.06.15
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 ATCHISON NICK;ROSS RON
分类号 G01R31/28;H01L21/66;(IPC1-7):G01R31/26 主分类号 G01R31/28
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