发明名称 MICROCOMPUTER SYSTEM AND ITS PROCESSING ORDER INSPECTING METHOD
摘要 PROBLEM TO BE SOLVED: To unnecessitate production of a debug circuit again even when a flash memory, a DRAM or an SRAM is used as an emulation memory by providing a debug circuit corresponding to the control system of various kinds of memories. SOLUTION: A debug circuit 15 has a download function for reading and writing a program to an emulation memory 16. A download control circuit capable of controlling a plurality of kinds of emulation memories incorporated in the circuit 15 executes a read/write operation to the memory 16 through a GD bus 8a. Instead of a CPU 11, the download control circuit is connected to an address bus 5a and a data bus 5b. A read/write command to the memory 16 is issued from an external emulator through a private input/output terminal 8 and the download control circuit incorporated in the circuit 15.
申请公布号 JP2001084157(A) 申请公布日期 2001.03.30
申请号 JP19990262049 申请日期 1999.09.16
申请人 MITSUBISHI ELECTRIC CORP 发明人 YOKOYAMA MASAHIRO;KANZAKI TERUAKI
分类号 G06F11/22 主分类号 G06F11/22
代理机构 代理人
主权项
地址