发明名称 |
Huffman decoder architecture for high speed operation and reduced memory |
摘要 |
Various Huffman decoder architectures are presented. By these decoder architectures, more than one codeword in a stream of Huffman-coded data units may be decoded into more than one token in a single decoding operation on average. An efficient memory organization which is useful in many of these decoder architectures is also presented. |
申请公布号 |
GB2269070(B) |
申请公布日期 |
1996.04.24 |
申请号 |
GB19930008583 |
申请日期 |
1993.04.26 |
申请人 |
* RICOH COMPANY LIMITED |
发明人 |
JAMES * ALLEN;MARTIN P * BOLIEK;EDWARD L * SCHWARTZ;DAVID * BEDNASH |
分类号 |
H03M7/40;G06T9/00;H03M7/42;H04N7/26;H04N7/30;(IPC1-7):H03M7/40;H04N1/41 |
主分类号 |
H03M7/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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