| 摘要 |
PROBLEM TO BE SOLVED: To provide a data processor that has a small circuit scale, and can highly efficiently avoid overflow and underflow of an FIFO circuit. SOLUTION: This data processor outputs remainder increase and decrease notification signals, that indicate the increase and decrease of remainder and consist of 1 bit from FIFO circuits 3441 and 3443 to an internal bus control circuit 32. In the internal bus control circuit 342, storage data is shifted to ward the MSB for setting 1 to the LSB, based on the remainder increase notification signal, and the storage data is shifted to the LSB for setting '0' to the MSB, based on the remainder increase notification signal. Then, a bit with '0' is retrieved from the LSB of the storage data, and it is decided whether FIFO circuits 3441 and 3443 read indication signals are outputted, based on the position of the bit retrieved.
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