| 摘要 |
PROBLEM TO BE SOLVED: To obtain a high-speed lockup circuit for a PLL that can attain a lockup operation at high speed with a comparatively simple configuration without causing deterioration in characteristic. SOLUTION: The PLL circuit is provided with a phase comparator 5 that compares the phase of a reference signal fREF with the phase of a comparison signal f0 and provides the output in response to its phase difference, a charge pump 6 that receives the output of the phase comparator 5, a low-pass filter that integrates the output of the charge pump 6, a voltage controlled oscillator 8 that receives the output of the low-pass filter 7 and a programmable divider 4 that frequency-divides the output of the voltage controlled oscillator 8 and gives the result to the phase comparator 5 as the comparison signal f0. In this case, pre-charging that adds a reference signal VREF 1 to a tuning signal VT of the voltage controlled oscillator 8 is conducted in response to set data SI to the programmable divider 4. |
