Address transition detect timing architecture for a simultaneous operation flash memory device

摘要

An address transition signal generator for a dual bank flash memory device is disclosed. The generator includes signal transition detectors which monitor control signals of the device for transitions in their logical values. Upon detection of a signal transition, the transition detectors send a signal across equidistant signal paths to bank address transition detect signal generator circuits. This results in simultaneous generation of the address transition detect signal from each of the bank address transition detect signal generator circuits.