发明名称 VERTICAL SYNCHRONIZING SIGNAL SEPARATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent the occurrence of bend in an output TV picture by not affecting a dual AFC circuit at the time of separating a composite synchronizing signal to which a copy guard signal is added. SOLUTION: This vertical synchronizing signal separation circuit is provided with a current source 1, a current source 3 which supplies a current larger than that of the current source 1, a capacitor C1 for integration of the difference of the current values between current sources 1 and 3, and a comparator 12 for comparison between the voltage Vc of the capacitor C1 and a second reference voltage V2 and generates and outputs a vertical output pulse PV in the case that the voltage Vc of the capacitor C1 exceeds the second reference voltage V2. In this case, a current source 2 which supplies a current smaller than that of the current source 1, a switch SW1 which performs switching between the outputs of the current sources 1 and 2 to output the output of the current source 1 or 2 to the collector side of a transistor TR2, and a switch control part 31 which switches the switch SW1 to the side of the current source 2 in the period from the reset of vertical synchronization to the termination of the vertical blanking period are provided.
申请公布号 JP2001078054(A) 申请公布日期 2001.03.23
申请号 JP19990254899 申请日期 1999.09.08
申请人 MITSUBISHI ELECTRIC CORP 发明人 ITABI TERUAKI
分类号 H04N5/10;H04N5/913;(IPC1-7):H04N5/10 主分类号 H04N5/10
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