| 摘要 |
A microprocessor is described having an arithmetic unit 8 that includes a dedicated hardware divider. The hardware divider is responsive to a plurality of different divide instruction codes to generate respective multi-bit portions of a quotient. Each divide instruction can be early terminated when the partial remainder is detected as being zero. Furthermore, subsequent divide instructions to calculate the remaining bits of the quotient can be skipped in response to a flag (Zflag) set within a current programming status register 28. In the described embodiment, a 32-bit divisor and 64-bit dividend serve to produce a 32-bit quotient and a 32-bit remainder. The generation of the 32-bit quotient takes place in response to four different divide instruction codes each responsible for generating a respective 8-bit portion of the quotient. |
