发明名称 APPARATUS FOR OUTPUTTING FRAME DATA OF ATM SWITCH
摘要 PURPOSE: An apparatus for outputting frame data of an ATM(Asynchronous Transfer Mode) switch is provided to be easily applied to a re-synchronization algorithm by decreasing parameters necessary for wireless environment as a frame head byte, a link control channel assignment byte, and an order line channel assignment byte, using the decreased parameters, and selecting 8 sub-frame headers in one frame, and assigning 1 byte before every sub-frame. CONSTITUTION: A frame header generator and frame data output unit(1) receives a frame synchronous enable signal, generates a frame header, and outputs frame data. A cell data output unit(2) outputs cell data according to the input of a cell enable signal. A sub-frame header generator and sub-frame data output unit(3) receives a sub-frame synchronous enable signal, generates a sub-frame header, and outputs sub-frame data. An LCC(Link Control Channel) data output unit(4) outputs LCC data according to the input of an LCC enable signal. An OWC(Order Wire Channel) data output unit(5) outputs OWC data according to the input of an OWC enable signal. A preliminary data output unit(6) outputs preliminary data according to the input of a preliminary enable signal. The first multiplexer(7) successively selects outputs of the frame header generator and frame data output unit(1), the cell data output unit(2), the OWC data output unit(5), and the preliminary data output unit(6) according to the input of selectors(S1,S2) and outputs the selected output. The second multiplexer(8) successively selects output data of the cell data output unit(2), the sub-frame header generator and sub-frame data output unit(3), the LCC data output unit(4), the OWC data output unit(5), and the preliminary data output unit(6) according to the input of selectors(S3-S5) and outputs the selected output. The third multiplexer(9) multiplexes outputs of the first and second multiplexers(7,8). A control signal generator(10) receives a square wave and outputs a control signal to each unit.
申请公布号 KR100292200(B1) 申请公布日期 2001.03.21
申请号 KR19970071193 申请日期 1997.12.20
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, DAE SIK
分类号 H04L12/28;(IPC1-7):H04L12/28 主分类号 H04L12/28
代理机构 代理人
主权项
地址