| 摘要 |
PROBLEM TO BE SOLVED: To attain a high operating speed for a semiconductor integrated circuit with low power consumption. SOLUTION: A CMOS circuit 108 uses a power level LVDD resulting from stepping down a power level VDD by a power level drop circuit 106 for a power supply level, the power supply level VDD is given to a back gate of a PMOS 109 of a CMOS inverter circuit e.g. being a component of the CMOS circuit 108, and the impurity concentration of a base or a well layer forming the PMOS 109 receiving a bias is reduced so as to adjust a threshold voltage by taking increase in an absolute value of the threshold voltage Vtp of the PMOS 109 due to the back gate effect caused by giving the power supply level VDD to the back gate of the PMOS 109 into account. The adjusted voltage is the same as a threshold voltage of the PMOS receiving no bias for the operation of the circuit.
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