发明名称 |
SEMICONDUCTOR DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To reduce the scattering or deviation of the parallel interface operation timing of a plurality of interface circuits. SOLUTION: A plurality of interface circuits to be interfaced to the outside in parallel are divided into a plurality of groups OAL and OAR, and a timing signal for controlling an interface operation is supplied in series from a timing control line W6 in group units. The difference (skew) of the propagation delay of the timing signal between the base and end edges of timing control wiring can be reduced as compared with a case where a plurality of interface circuits used for parallel interface to the outside are not divided into groups and are bound at one point for supplying the timing signal in series with common timing control wiring, thus reducing the skew of the timing signal for each group.
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申请公布号 |
JP2001067864(A) |
申请公布日期 |
2001.03.16 |
申请号 |
JP19990245822 |
申请日期 |
1999.08.31 |
申请人 |
HITACHI LTD;HITACHI DEVICE ENG CO LTD |
发明人 |
CHIGASAKI HIDEO;MIYASHITA HIROMOTO;YAHATA HIDEJI;HORIGUCHI SHINJI |
分类号 |
G11C11/401;G11C11/407;H01L21/822;H01L27/04;(IPC1-7):G11C11/401 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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