发明名称 Method and apparatus for connecting vertically stacked integrated circuit chips
摘要 Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metallizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metallizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metallizations, which are disposed in part on the bare insulative surface.
申请公布号 US6806559(B2) 申请公布日期 2004.10.19
申请号 US20020128728 申请日期 2002.04.22
申请人 IRVINE SENSORS CORPORATION 发明人 GANN KEITH D.;ALBERT DOUGLAS M.
分类号 H01L21/98;H01L25/10;(IPC1-7):H01L23/495;H01L21/48;H01R43/00;H05K5/02 主分类号 H01L21/98
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