发明名称 |
PARALLEL FLOATING POINT ROUNDING METHOD AND OPERATION UNIT |
摘要 |
PURPOSE: A parallel floating point rounding method and its operation unit is provided to process an addition and a rounding operation in a floating point addition unit by one step and eliminate a Sticky bit in a critical path so that it can reduce a time delay occurred at an alignment of exponential numbers and enhance a process speed of a floating point addition operation. CONSTITUTION: The method comprises steps of comparing exponent parts of a 1st operand and a 2nd operand input by a user, aligning a fractional part by a difference between the exponent parts, logically adding a Sticky bit to the fractional part, executing an addition and a subtraction operation, executing 4 mode rounding operation on the addition and the subtraction result, selectively outputting the rounded value, and normalizing the selectively output rounded value. The Sticky bit is generated in the addition/subtraction and the rounding process, and has no effect on the critical path.
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申请公布号 |
KR20010018956(A) |
申请公布日期 |
2001.03.15 |
申请号 |
KR19990035123 |
申请日期 |
1999.08.24 |
申请人 |
HAN, TACK DON;PARK, WOO CHAN |
发明人 |
HAN, TACK DON;JUNG, CHEOL HO;PARK, WOO CHAN |
分类号 |
G06F7/49;(IPC1-7):G06F7/49 |
主分类号 |
G06F7/49 |
代理机构 |
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