| 摘要 |
PURPOSE: To provide a clock analyzing device which can efficiently analyzes the delay value or skew value of the layout pattern of a semiconductor integrated circuit, provides supplementary information showing the presence of a part where the delay value or skew value is large, and shorten the design time of the semiconductor integrated circuit. CONSTITUTION: Circuit connection information, transistor characteristic information, and control information are stored in memories 1 to 3, and read out and edited by a preprocessing part 4 so that simulation can be performed, a simulation execution part 5 simulates circuit operation, and a postprocessing part 6 calculates the delay value from an input node to a terminal node, differences in delay value among respective terminal nodes, and a rise/fall time, and displays the analysis results out on a two-dimensional distribution chart.
|
