| 摘要 |
A data processing apparatus includes a first circuit unit operating with first clocks of a predetermined cycle, a second circuit unit operating with second clocks of a predetermined cycle different from the first clock cycle, and a first circuit block which generates and outputs a train of pulses in accordance with the first clock cycle. The second circuit unit includes a second circuit block which receives the train of pulses output from the first circuit block, and samples the train of pulses using the second clock as a sampling signal, to thereby output the sampled train of pulses; a third circuit block which receives the train of pulses output from the second circuit block, and delays the train of pulses by a predetermined number of clocks in response to the second clock, to thereby output the delayed train of pulses; and a fourth circuit block which receives the train of pulses output from the second circuit block and the train of pulses output from the third circuit block, and effects a predetermined processing with respect to both trains of pulses, to thereby generate and output a train of pulses with a cycle approximately equal to the first clock cycle. efficiently realizes data transfer processings between circuit units operating with different clock cycles.
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