| 摘要 |
A state machine operates in synchronization with a reference clock signal (110) to switch between n numbers of states and maintain any one of these states. Every time a condition for transition to each of the n numbers of states is satisfied, a signal output circuit (100) makes one of n numbers of transition condition satisfying signals (111W, 111Z, 111Y . . . ) active and outputs it. One of a plurality of D-type flip-flops (101-1, 101-2, 101-k . . . ) makes active any one of nu numbers of state signals (W, Z, Y . . . ) indicating the corresponding n numbers of states, and holds the corresponding one state. A synchronization pulse generation circuit (102) generates a one-shot synchronization pulse signal (112) in synchronization with the reference clock signal (110), when a transition condition for transition to one state is satisfied. When a one-shot synchronization pulse signal (112) is input to the D-type flip-flop (101-k) and also the condition for transition to state Y has been satisfied, the state Y is held during the period from after the establishment of the condition for transition to the state Y, until a condition for transition to another state such as W or Z is satisfied.
|
