| 摘要 |
A PLL includes a plurality of phase comparators, and when one of them is locked in, the outputs of all the phase comparators except the locked one are opened to save power. At an instant close to a lock-in, the magnitude of the error current output from a charge pump (109) connected with the phase comparator is reduced to preventing unlocking. Further, the time constant of a low frequency filter (220) which receives the output from the charge pump connected with the phase comparator is changed with the change in the number of active phase comparators (212-219) to save power consumption and increase stability and convergence speed. Distribution means (318), rather than individual frequency dividers, is provided for the phase comparators to facilitate making the PLL into an LSI.
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