发明名称 Method for forming polycide dual gate
摘要 A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an alpha-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.
申请公布号 US6197672(B1) 申请公布日期 2001.03.06
申请号 US19980208271 申请日期 1998.12.08
申请人 UNITED MICROELECTRONICS CORP. 发明人 LIN YUNG-CHANG;CHEN TUNG-PO;CHEN JACOB
分类号 H01L21/28;H01L29/49;(IPC1-7):H01L21/320 主分类号 H01L21/28
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