| 摘要 |
A circuit arrangement for interconnecting electronic components such as integrated circuit devices, chip packages and/or circuit boards includes signal, first fixed potential (e.g., power) and second fixed potential (e.g., ground) interconnects arranged into an interconnection layout pattern that offers greater flexibility, performance and cost effectiveness than conventional patterns. In some implementations, the interconnection layout pattern incorporates one or more tiles of interconnects, with each tile defining a plurality of interconnect positions arranged into at least three rows and at least four columns. For each tile, a signal interconnect is disposed at each of the three interconnect positions in each of the first and fourth columns, and one each of a signal interconnect, a first fixed potential interconnect and a second fixed potential interconnect are disposed in each of the second and third columns. In other implementations, the interconnection layout pattern arranges the interconnects into an array that defines interior and boundary interconnect positions, with each interconnect disposed at an interior interconnect position bordered on each side by another interconnect in the array, and with each signal interconnect disposed at an interior interconnect position in the array immediately adjacent to at least one first fixed potential interconnect and at least one second fixed potential interconnect.
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