| 摘要 |
PURPOSE: A pipeline counter for semiconductor memory chip is provided to enable a stable operation in a simplified structure even at high frequency, and reduce power consumption. CONSTITUTION: A pipeline counter includes three sections of control(30), enable(32), and multiple pipelines(34,36,38). The controller(30) receives a main clock signal(Clock) and an output enable signal(Out_Enable) from external sources, and produces control signals controlling the entire operation of the counter. The enable section(32) produces an enable signal according to the control signals from the controller(30). Each of the multiple pipelines(34,36,38) produces a pipeline counter signal(PCNT(0)-PCNT(2)) after receiving the enable control signal(en0-en2) respectively.
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