| 摘要 |
<p>A hybrid cardiac pacemaker in which the operation of the device is controlled by hardware-based controller as supervised by a microprocessor-based controller. The hardware-based controller comprises a plurality of timers that expire when they reach timer limit values stored in registers updatable by the microprocessor, and a combinational logic array for causing the device to generate pace outputs in accordance with timer expirations and sense signals. The combinational logic array may operate the pacemaker in a number of programmed modes in accordance with a mode value stored in a mode control register by the microprocessor.</p> |
