| 摘要 |
A memory device including a plurality of sense amplifiers distributed about an integrated circuit chip, where each sense amplifier has a power node for receiving current. A conductor couples the power nodes of a number of sense amplifiers together. A low-impedance power supply conductor extends to each sense amplifier and a local drive transistor is provided for each sense amplifier. A timer unit generates an output signal controlling the local drive transistors. A first component within the timer unit causes the output to change from a first logic level towards a second logic level at a first rate while a second component within the timer unit causes the output to change at a second rate, wherein the second rate is greater than the first rate.
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