| 摘要 |
A data corruption indicator circuit for providing error free data transfer between a first device and a second device, clocked by different clock signals, is implemented. The data corruption indicator circuit can allow for faster throughput than the described prior art and provides a circuitry for detecting corrupt data. The data corruption indicator circuit provides a clocked data ready signal that updates a status lip-flop and a delayed data ready signal that updates a plurality of data flip-flops and a potential corruption flip-flop. Additionally, the delayed data ready signal may be used as an interrupt signal to notify the second device that data is available for transfer. The delay between the clocked data ready signal and the delayed data ready signal is such that a hazard cannot exist for the data signal and the status signal simultaneously. The failsafe nature of the invention is that while the status signal may indicate corrupt data when the data is actually valid, it will not indicate valid data when the data is corrupt.
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