发明名称 |
Method and an auxiliary circuit for preventing the triggering of a parasitic transistor in an output stage of an electronic circuit |
摘要 |
A method, and related circuit, prevent the triggering of a parasitic transistor in an output stage of an electronic circuit. The stage includes a transistor pair with at least one transistor of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor having a terminal connected to the body terminal. The method includes the steps of providing a capacitor connected between the body and source terminals of the PMOS transistor; and using a control circuit to suppress the body effect of the pull-up PMOS transistor.
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申请公布号 |
US6194948(B1) |
申请公布日期 |
2001.02.27 |
申请号 |
US19980106583 |
申请日期 |
1998.06.29 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
SCIAN ENRICO;MARTIGNONI FABRIZIO;DEPETRO RICCARDO |
分类号 |
G11C11/413;G05F3/20;H01L21/8238;H01L27/02;H01L27/092;H03K17/08;H03K17/687;H03K19/003;H03K19/0175;(IPC1-7):H03K17/30 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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