| 摘要 |
PROBLEM TO BE SOLVED: To reduce the total number of frequency divisions by using an internally used frequency converter and to enable the broad band of PLLs and the low noise of the PLLs by inputting an intermediate signal to the frequency converter as a local signal and inputting the same intermediate signal to a PLL part as a reference signal. SOLUTION: A 1st PLL circuit 20 receives a preliminarily given reference signal F1 and generates an intermediate signal F2, and a 2nd PLL circuit 30 receives an intermediate signal F2 being an output of the circuit 20 and obtains a synthesizer output F3 with the signal as reference. In the circuit 30, a PLL part 40 has the same configuration as the circuit 20, the signal F2 is also inputted to the part 40 as a reference signal, and meanwhile, the signal F2 is also inputted to a frequency converter 37 as a local signal. With such a configuration, the total number of frequency divisions can be reduced by using the internally used frequency converter 37 because the two PLL circuits are provided, the band of the PLLs can be wide and the noise of the PLLs can be made low. |
