发明名称 ON-CHIP MULTIPLEXER
摘要 PROBLEM TO BE SOLVED: To make control between multiple processor fast and high in performance by arranging a couple of processors among the processors symmetrically about a specific straight axis or specific origin on a chip plane. SOLUTION: An instruction processor IP10 and IP20 are arranged symmetrically about a virtual straight axis 40 on the chip plane and further an SU 30 of a storage control unit is arranged in an area containing the straight axis 40. Further, GSs 32, 33 as common caches of the instruction processor IP10, IP20 and common I/Os 34, 35 of the IPs 10 and 20 are arranged symmetrically about the straight axis 40 and also symmetrically about a straight axis 41. Further, double units have instruction units IUs 11, 12 and IUs 21, 22, general arithmetic unit GUs 14, 15 and GUs 24, 25, and floating-point unit FUs 16, 17 and FUs 26, 27 arranged symmetrically about the straight axis 41.
申请公布号 JP2001051957(A) 申请公布日期 2001.02.23
申请号 JP19990221728 申请日期 1999.08.04
申请人 HITACHI LTD 发明人 KATO TAKESHI;YAMAMOTO MICHITAKA;KAINO HIROMICHI;SHIMIZU TERUHISA;OBAYASHI MASAYUKI;YAMASHITA HIROKI;MASUDA NOBORU;SAITO TATSUYA
分类号 G06F15/16;G06F15/00;G06F15/80;(IPC1-7):G06F15/16 主分类号 G06F15/16
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