| 摘要 |
A clock control signal and an output enable signal generating circuit of a semiconductor memory device includes a first control signal and clock control signal generating circuit, a second control signal generating circuit a write pass through signal generating circuit for generating a write pass through signal in the read command cycle in case write and read commands are sequentially input in a pipeline operation, a third control signal generating circuit for generating a third control signal for detecting a shift from a low impedance of low level to a high impedance of high level in an operation of double cycle deselect function, and for generating the third control signal in a deselect or write command cycle when read, deselect commands or read, write commands are sequentially input in an operation of single cycle deselect function; and an output enable signal generating circuit to generating an output enable signal in response to an output enable control signal in a flow through operation, for generating the output enable signal of high level in response to the second control signal and a signal inverted from the first control signal and for generating the output enable signal of low level in response to the third control signal or the second control signal in a pipeline operation.
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