发明名称 |
Robust latchup-immune CMOS structure |
摘要 |
A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.
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申请公布号 |
US6190954(B1) |
申请公布日期 |
2001.02.20 |
申请号 |
US19990229381 |
申请日期 |
1999.01.11 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
LEE JIAN-HSING;CHEN SHUI-HUNG;SHIH JIAW REN |
分类号 |
H01L21/8238;H01L27/092;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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