| 摘要 |
PROBLEM TO BE SOLVED: To easily and economically implement a mixed circuit consisting of a memory cell and a peripheral circuit by enabling reduction of a cell area without affecting accuracy and decreasing the number of wiring layers. SOLUTION: A bit line BL, a word line WL, a control gate line CGL, a capacitor CAP in which a first electrode TA are connected to the word line WL, a read transistor TR consisting of an nMOS connected between the bit line BL and a predetermined potential point and in which a gate electrode is connected to a second electrode TB of the capacitor CAP, and a write transistor TW consisting of an nMOS connected between the bit line BL and the second electrode TB of the capacitor CAP and in which the gate electrode is connected to the control gate line CGL, are provided. |
