发明名称 Forming a semi-recessed capacitor structure in an inter-polysilicon dielectric
摘要 A method for forming a semi-recessed capacitor structure in an inter-polysilicon dielectric is disclosed. The method includes the following steps. First of all, a first oxide layer is formed. A first nitride layer is formed. Then, a second oxide layer is formed. Again, a second nitride layer is formed. Next, a third oxide layer is formed. Then, a first photoresist is formed. A portion of the third oxide layer, a portion of the second nitride layer, a portion of the second oxide layer and a portion of the first nitride layer are all etched. A first polysilicon layer is formed. Then, a portion of the first polysilicon layer is etched. A dielectric layer is formed. Next, a second photoresist layer is formed. Then, a portion of the dielectric layer, a portion of the third oxide layer, of the second nitride layer and some of the second oxide layer are etched. Then, a second polysilicon layer is deposited. Next, a portion of the second polysilicon layer is etched back. Finally, the dielectric layer and the third oxide layer are etched. Thus, the second polysilicon layer is remained into the second nitride layer and the second oxide layer, whereby completing the capacitor structure having the semi-recessed structure.
申请公布号 US6187626(B1) 申请公布日期 2001.02.13
申请号 US20000495244 申请日期 2000.01.31
申请人 UNITED MICROELECTRONICS CORP. 发明人 SZE JHY-JYI
分类号 H01L21/02;H01L21/311;H01L21/768;H01L21/8242;(IPC1-7):H01L21/824 主分类号 H01L21/02
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