| 摘要 |
<p>PROBLEM TO BE SOLVED: To generate a synchronizing signal with stable data demodulation components even when the data demodulation components on which power supply components are superimposed is inputted by controlling a phase of an output signal based on a phase correction signal by an output signal generating circuit and outputting the output signal with the controlled phase as the synchronizing signal. SOLUTION: Phases are converged into a state that starting timing of a cycle of a data demodulating component W3 and starting timing of a cycle of a data carrier wave W5 are equivalent, namely, a state that the phases of the data demodulation component W3 and the data carrier wave W5 are equivalent. When the data carrier wave W5 with the same phase and cycle with the data demodulation component W3 is outputted from a synchronizing signal generator 13, an exclusive OR value between the data carrier wave W5 and the data demodulation component W3 is outputted as a reproduced data signal from a first exclusive OR circuit 14. Periods of high and low levels of the reproduced data signal W6 are compared by every cycle of the data carrier wave W5 by a one-bit width counter 15.</p> |
