| 摘要 |
PROBLEM TO BE SOLVED: To enable monitoring all defective contents in the outside in principle by providing a data storing means storing data in a normal memory, a comparing means outputting a comparison signal between a memory test result signal and data of the data storing means, a control means controlling so that the comparison signal is outputted to the outside, in a BIST circuit. SOLUTION: A BIST circuit B10 generates a test vector from an address generating circuit A21 and a data generating circuit WD22, and operates a memory 40. A comparing circuit CP12 outputs a compared result signal TR between an output signal from the memory M40 and an output signal TRD from a verification data generating circuit RD23. When defect exists in the memory 40, the comparison signal TR is made '1'. When the compared result signal is made '1', a control circuit CT11 makes a control signal TCT1 invalid, and makes a shift register control signal TCT2 valid. A shift register SR13 outputs a test result of the memory 40 in which the defect exists to an output signal TO.
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